SAMPLE AND HOLD CIRCUIT

SAMPLE AND HOLD CIRCUIT


AIM:
To set up a sample and hold circuit and to study its operation.


COMPENENTS AND EQUIPMENTS REQUIRED:
Op-amp, function generator, CRO, BFW 10, resistors and capacitors.


THEORY:
A Sample and Hold circuit samples an input signal and holds on to its last sampled value until the input is sampled again. This type of circuit is very useful in digital interfacing and analog to digital and pulse code modulation systems. One of the simplest practical sample and Hold circuit configuration is shown in the figure. The n-channel
E-MOSFET works as a switch and controlled by the control voltage Vc and the capacitor C stores the charge. The analog signal Vs to be sampled is applied to the drain of
E-MOSFET and the control voltage Vc is applied to its gate. When Vc is positive, the E-MOSFET turns on and the capacitor C charges to the instantaneous value of input Vs with a time constant [Ro+rDS(on). Here Ro is the o/p resistance of the voltage follower A1 and rds(on) is the resistance of the MOSFET when on. Thus the i/p voltage Vs appears across the capacitor C and then at the o/p through the voltage follower A2.
During the time when control voltage Vc is zero, the E-MOSFET is OFF. The capacitor C is now facing the high input impedance of voltage follower A2 and hence cannot discharge. The capacitor holds the voltage across it. The time period Ts, the time during which the voltage across the capacitor is equal to input voltage is called Sample period. The time period TH of Vc during which the voltage across the capacitor is held constant is called Hold period. The frequency of the control voltage should be kept higher than (at least twice) the input so as to retrieve the input from output waveform.



PROCEDURE:
1. Connections are made as shown in the figure.
2. Feed pulse to the input of this circuit and note down the output.



RESULT:
Sample and hold circuit is setup and studied.